P. Oldiges

Modeling line edge roughness effects in sub 100 nanometer gate length devices

P. Oldiges, Qimghuamg Lin, Karen Petrillo et al. · 2002 · 112 citations

Device Modeling, Electrical Engineering, Semiconductor Device +13

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta et al. · 2014 · 97 citations

Engineering, Vlsi Design, Finfet Technology +18

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

K. Rim, Robert E. Anderson, D. Boyd et al. · Solid-State Electronics · 2003 · 91 citations

Electrical Engineering, Engineering, Nanoelectronics +6

CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

Kaushik Nayak, Mohit Bajaj, Aniruddha Konar et al. · IEEE Transactions on Electron Devices · 2014 · 77 citations

Device Modeling, Electrical Engineering, Si Nanowire +10

Channel doping impact on FinFETs for 22nm and beyond

C.-H. Lin, R. Kambhampati, Robert J. Miller et al. · 2012 · 66 citations