Karen Petrillo

Modeling line edge roughness effects in sub 100 nanometer gate length devices

P. Oldiges, Qimghuamg Lin, Karen Petrillo et al. · 2002 · 112 citations

Device Modeling, Electrical Engineering, Semiconductor Device +13

Sub-μm, planarized, Nb-AlO<i>x</i>-Nb Josephson process for 125 mm wafers developed in partnership with Si technology

M. B. Ketchen, D.J. Pearson, A. W. Kleinsasser et al. · Applied Physics Letters · 1991 · 107 citations

Superconducting Material, Engineering, Si Technology +17

Evaluation of EUV resist materials for use at the 32 nm half-pitch node

Thomas I. Wallow, Craig Higgins, Robert L. Brainard et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2008 · 107 citations

Short Wavelength Optic, Optical Materials, Engineering +24

A high-performance 0.25- mu m CMOS technology. II. Technology

B. Davari, Wei‐Hsu Chang, Karen Petrillo et al. · IEEE Transactions on Electron Devices · 1992 · 102 citations

Low-power Electronics, Electrical Engineering, Dual Poly Gates +15

Environmentally stable chemical amplification positive resist: principle, chemistry, contamination resistance, and lithographic feasibility.

Hiroshi Itô, Greg Breyta, Don Hofer et al. · Journal of Photopolymer Science and Technology · 1994 · 96 citations · Full text