C. Caillat

Evolution of materials technology for stacked-capacitors in 65nm embedded-DRAM

E. Gerritsen, N. Emonet, C. Caillat et al. · Solid-State Electronics · 2005 · 99 citations

Engineering, Materials Engineering, Materials Science +12

3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

C. Caillat, K.L. Beaman, Andrew Bicksler et al. · 2017 · 50 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF ₂ pockets

S. Deleonibus, C. Caillat, G. Guégan et al. · IEEE Electron Device Letters · 2000 · 34 citations

Engineering, Electrical Engineering, Electronic Materials +14

Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM

Luciano M. Almeida, K. R. A. Sasaki, C. Caillat et al. · Solid-State Electronics · 2013 · 29 citations

Computing, Computer Systems, Optimization +2

Highly Reliable TiN/ZrO2/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies

A. Berthelot, C. Caillat, V. Huard et al. · Proceedings of the European Solid State Device Research Conference · 2006 · 27 citations

Engineering, Electrical Engineering, Materials Science +17