3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

Abstract

The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation. This paper reviews the main features of GIDL-assisted body biasing and GIDL optimization methods ensuring the best erase effectiveness and variability control. Finally, the excellent reliability of the selector gate devices over Program/Erase cycles is demonstrated, proving the reliability of this technique.