X. Wang

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding

F. Liu, R. Yu, Anthony Young et al. · 2008 · 118 citations

Engineering, Cu Beol, Interconnect (Integrated Circuits) +18

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, S. Samavedam, Vijay Narayanan et al. · 2008 · 112 citations

Low-power Electronics, Low Power Applications, Electrical Engineering +14

FinFET performance advantage at 22nm: An AC perspective

Michael Guillorn, Josephine Chang, A. Bryant et al. · 2008 · 83 citations

Device Modeling, Electrical Engineering, Engineering +11

Investigation of FinFET Devices for 32nm Technologies and Beyond

Huiling Shang, L. Chang, X. Wang et al. · 2006 · 53 citations

Electrical Engineering, Engineering, Vlsi Design +11