2008 · 118 citations · 0 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsPackaging DesignSemiconductor DevicesAdhesive BondingChip PackagingIntegrated Circuit DesignIntegrated Circuit DevicesInterconnect TechnologyWafer Bonding3D Integrated CircuitsDie-to-wafer BondingPhysical PropertiesRlc CircuitsThree-dimensional IntegrationThrough-silicon ViasWafer ThinningWafer-to-wafer Bonding
The process uses fine‑pitch tungsten TSVs (5 µm pitch, 1.5 µm critical dimension, 17:1 aspect ratio) bonded via a hybrid Cu/adhesive transfer‑join technique, with the top wafer thinned to 20 µm and a Cu backside BEOL. The TSVs and bonded interconnects exhibit RLC characteristics that meet power delivery and high‑speed signaling requirements for high‑performance 3D systems.
A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 mum), small critical dimension (1.5 mum), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer. The process also features thinning of the top wafer to 20 mum and a Cu backside BEOL on the thinned top wafer. The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems.