X. Li

A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding

F. Liu, R. Yu, Anthony Young et al. · 2008 · 118 citations

Engineering, Electrical Engineering, Materials Science +17

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

Kangguo Cheng, A. Khakifirooz, P. Kulkarni et al. · Symposium on VLSI Technology · 2006 · 31 citations

Engineering, Electrical Engineering, Materials Science +17

A 0.127 μm<sup>2</sup> High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

G. Wang, K. Cheng, H. Ho et al. · 2006 · 14 citations

Engineering, Computer Engineering, Electrical Engineering +17