Michael Aquilino

High performance 14nm SOI FinFET CMOS technology with 0.0174µm ² embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +9

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, S. Samavedam, Vijay Narayanan et al. · 2008 · 113 citations

Engineering, Computer Engineering, Electrical Engineering +16

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 7nm CMOS technology platform for mobile and high performance compute application

B. Jagannathan, Akihisa Ogino, D. Jaeger et al. · 2017 · 60 citations

Engineering, Computer Engineering, Electrical Engineering +14

Hybrid low‐ <i>k</i> spacer scheme for advanced FinFET technology parasitic capacitance reduction

Man Gu, X. Wang, W. Li et al. · Electronics Letters · 2020 · 20 citations

Engineering, Electrical Engineering, Materials Science +17