Estimating Single-Event Logic Cross Sections in Advanced Technologies

R. C. Quinn, J. S. Kauppila, Kevin M. Warren, +8

IEEE Transactions on Nuclear Science

Event-driven ArchitectureCross SectionEngineeringVlsi DesignComputer Architecture +20

Utilizing device stacking for area efficient hardened SOI flip-flop designs

J. S. Kauppila, T. D. Loveless, R. C. Quinn, +7

Hardware SecurityTilt AngleElectrical EngineeringSoft Error Cross-sectionEngineering +13

Angular Effects on Single-Event Mechanisms in Bulk FinFET Technologies

Patrick Nsengiyumva, L. W. Massengill, J. S. Kauppila, +10

IEEE Transactions on Nuclear Science

Device ModelingElectrical EngineeringAngular EffectsEngineeringAdvanced Packaging (Semiconductors) +11

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

J. A. Maharrey, R. C. Quinn, T. D. Loveless, +9

IEEE Transactions on Nuclear Science

EngineeringSilicon On InsulatorIon ImplantationDevice VariantsSet Pulse Distributions +16

The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops

Dennis R. Ball, Michael L. Alles, J. S. Kauppila, +9

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignIntegrated CircuitsSilicon On InsulatorSet Pulsewidths +16

Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

R. C. Harrington, J. A. Maharrey, J. S. Kauppila, +6

IEEE Transactions on Nuclear Science

Device ModelingElectrical EngineeringSemiconductor DeviceEngineeringTransistor Variant +11

Geometry-Aware Single-Event Enabled Compact Models for Sub-50 nm Partially Depleted Silicon-on-Insulator Technologies

J. S. Kauppila, L. W. Massengill, Dennis R. Ball, +6

IEEE Transactions on Nuclear Science

Device ModelingElectrical EngineeringCompact ModelEngineeringVlsi Design +13

Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

J. A. Maharrey, J. S. Kauppila, R. C. Harrington, +7

IEEE Transactions on Nuclear Science

Set DurationEngineeringVlsi DesignPower Optimization (Eda)Set Mitigation Techniques +15

Exploiting Parallelism and Heterogeneity in a Radiation Effects Test Vehicle for Efficient Single-Event Characterization of Nanoscale Circuits

J. S. Kauppila, J. A. Maharrey, R. C. Harrington, +7

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignComputer ArchitectureEfficient TestabilityHardware Security +21

Dual-Interlocked Logic for Single-Event Transient Mitigation

J. A. Maharrey, J. S. Kauppila, R. C. Harrington, +7

IEEE Transactions on Nuclear Science

Event-driven ArchitectureEngineeringVlsi DesignLogic FamilyComputer Architecture +16