Utilizing device stacking for area efficient hardened SOI flip-flop designs

Abstract

D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to a heavy-ion tested tilt angle of 55°, and greater than one order of magnitude decrease in cross-section for a heavy-ion tested tilt angle of 75° with less than 50% area penalty compared to unhardened D-flip-flop designs.