Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

Mircea Dusa, John Quaedackers, Olaf F. A. Larsen, +12

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Wafer Scale ProcessingEngineeringElectron-beam LithographyBeam LithographyMicrofabrication +11

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Mireille Maenhoudt, Janko Versluijs, Herbert Struyf, +2

Optical Microlithography XVIII

Minimum PitchElectrical EngineeringDouble Patterning SchemeEngineeringElectron-beam Lithography +8

Double patterning for 32nm and below: an update

Jo Finders, Mircea Dusa, Bert Vleeming, +5

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Cdu ControlPhysical Design (Electronics)Array ComputingEngineeringElectron-beam Lithography +13

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

Julien Beynet, Patrick Wong, Andy Miller, +9

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Novel aberration monitor for optical lithography

Peter Dirksen, C.A.H. Juffermans, Rudy J. M. Pellens, +2

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Circular Phase ObjectOptical MaterialsEngineeringMicroscopyOptic Design +17

Printing the metal and contact layers for the 32- and 22-nm node: comparing positive and negative tone development process

Lieve Van Look, Joost Bekaert, Vincent Truffert, +6

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Contact PatterningEngineeringElectron-beam LithographyComputational IlluminationBeam Lithography +19

Alternative process schemes for double patterning that eliminate the intermediate etch step

Mireille Maenhoudt, Roel Gronheid, N. D. Stepanenko, +2

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Electrical EngineeringAlternative Process SchemesEngineeringVlsi DesignCircuit Design +13

Lithography Options for the 32 nm Half Pitch Node and Beyond

Kurt Ronse, P. Jansen, Roel Gronheid, +6

IEEE Transactions on Circuits and Systems I Regular Papers

Optical MaterialsEngineeringElectron-beam LithographyMicroscopyWafer Scale Processing +17

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A. Nackaerts, Monique Ercken, S. Demuynck, +32

EngineeringVlsi DesignNode Applications6T-sram Cell BuildSemiconductor Device +14

Characterisation and integration feasibility of JSR’s low-k dielectric LKD-5109

Abhishek Das, Tetsuro Kokubo, Yoshiaki Furukawa, +20

Microelectronic Engineering

Electrical EngineeringEngineeringApplied PhysicsMicrowave EngineeringIntegration Feasibility +1