Thinned wafer multi-stack 3DI technology

Takayuki Ohba, Nobuhide Maeda, Hideki Kitada, +5

Microelectronic Engineering

3D Ic ArchitectureWafer Scale ProcessingEngineeringAdvanced Packaging (Semiconductors)Microfabrication +5

Advanced wafer thinning technology and feasibility test for 3D integration

Young Seok Kim, Nobuhide Maeda, Hideki Kitada, +7

Microelectronic Engineering

3D Ic ArchitectureWafer Scale ProcessingEngineeringDevice IntegrationAdvanced Packaging (Semiconductors) +8

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

T. Nakamura, Hideki Kitada, Y. Mizushima, +3

Electrical EngineeringEngineeringAdvanced Packaging (Semiconductors)MicrofabricationNanoelectronics +12

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

Y. S. Kim, Shuhei Kodama, Y. Mizushima, +8

EngineeringEmerging Memory TechnologyIntegrated Circuits40-Nm Node 2GbWafer Scale Processing +19

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

D. Diehl, Hideki Kitada, Noritoshi Maeda, +19

Microelectronic Engineering

3D Ic ArchitectureElectrical EngineeringWafer Scale ProcessingEngineeringAdvanced Packaging (Semiconductors) +6

The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

Hideki Kitada, Takashi Suzuki, T. Kimura, +13

Electrical EngineeringRc Delay VariabilityEngineeringVlsi DesignPhysical Design (Electronics) +12

Clinical characteristics of immunoglobulin IgG4-related sclerosing cholangitis: Comparison of cases with and without autoimmune pancreatitis in a large cohort

Itaru Naitoh, Terumi Kamisawa, Atsushi Tanaka, +200

Digestive and Liver Disease

Autoimmune DiseaseMedicineImmunologyGastroenterologyPathology +7

Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

Hideki Kitada, Nobuhide Maeda, Koji Fujimoto, +4

Japanese Journal of Applied Physics

EngineeringThin Film Process TechnologySilicon On InsulatorInterconnect (Integrated Circuits)Semiconductor Device +15

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

Y. S. Kim, A. Tsukune, Noritoshi Maeda, +10

EngineeringStrained TransistorsIntegrated CircuitsUltra Thin WaferInterconnect (Integrated Circuits) +16

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

Noritoshi Maeda, Y. S. Kim, Yukinobu Hikosaka, +9

Device WafersEngineeringTerabit MemoryThinning ProcessEmerging Memory Technology +19