Hideki Kitada

Thinned wafer multi-stack 3DI technology

Takayuki Ohba, Nobuhide Maeda, Hideki Kitada et al. · Microelectronic Engineering · 2009 · 94 citations

3D Ic Architecture, Wafer Scale Processing, Engineering +7

Advanced wafer thinning technology and feasibility test for 3D integration

Young Seok Kim, Nobuhide Maeda, Hideki Kitada et al. · Microelectronic Engineering · 2013 · 84 citations

3D Ic Architecture, Wafer Scale Processing, Engineering +10

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

T. Nakamura, Hideki Kitada, Y. Mizushima et al. · 2012 · 42 citations

Electrical Engineering, Engineering, Advanced Packaging (Semiconductors) +14

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

Y. S. Kim, Shuhei Kodama, Y. Mizushima et al. · 2014 · 33 citations

Engineering, Emerging Memory Technology, Integrated Circuits +21

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

D. Diehl, Hideki Kitada, Noritoshi Maeda et al. · Microelectronic Engineering · 2011 · 29 citations

3D Ic Architecture, Electrical Engineering, Wafer Scale Processing +8