Cu Wettability and Diffusion Barrier Property of Ru Thin Film for Cu Metallization

Hoon Kim, Toshihiko Koseki, Takayuki Ohba, +4

Journal of The Electrochemical Society

Materials ScienceElectromigration TechniqueEngineeringDiffusion ResistanceCorrosion +12

Thinned wafer multi-stack 3DI technology

Takayuki Ohba, Nobuhide Maeda, Hideki Kitada, +5

Microelectronic Engineering

3D Ic ArchitectureWafer Scale ProcessingEngineeringAdvanced Packaging (Semiconductors)Microfabrication +5

Advanced wafer thinning technology and feasibility test for 3D integration

Young Seok Kim, Nobuhide Maeda, Hideki Kitada, +7

Microelectronic Engineering

3D Ic ArchitectureWafer Scale ProcessingEngineeringDevice IntegrationAdvanced Packaging (Semiconductors) +8

Direct detection of grain boundary scattering in damascene Cu wires by nanoscale four-point probe resistance measurements

Yusuke Kitaoka, Takeshi Tono, Shinya Yoshimoto, +3

Applied Physics Letters

EngineeringMicroscopyDirect DetectionDamascene Cu WiresGrain Size +20

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Yoriko Mizushima, Young-Suk Kim, T. Nakamura, +4

Japanese Journal of Applied Physics

EngineeringMechanical EngineeringSurface IntegrityDefect ToleranceUltrathin Wafers +20

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

T. Nakamura, Hideki Kitada, Y. Mizushima, +3

Electrical EngineeringEngineeringAdvanced Packaging (Semiconductors)MicrofabricationNanoelectronics +12

Material Consideration on Ta, Mo, Ru, and Os as Glue Layer for Ultra Large Scale Integration Cu Interconnects

Hoon Kim, Yasushi Naito, Toshihiko Koseki, +5

Japanese Journal of Applied Physics

EngineeringCu Adhesion PropertyAdhesion PromoterBcc ElementsInterconnect (Integrated Circuits) +15

Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

Y. S. Kim, Shuhei Kodama, Y. Mizushima, +8

EngineeringEmerging Memory TechnologyIntegrated Circuits40-Nm Node 2GbWafer Scale Processing +19

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

D. Diehl, Hideki Kitada, Noritoshi Maeda, +19

Microelectronic Engineering

3D Ic ArchitectureElectrical EngineeringWafer Scale ProcessingEngineeringAdvanced Packaging (Semiconductors) +6

Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

Hideki Kitada, Nobuhide Maeda, Koji Fujimoto, +4

Japanese Journal of Applied Physics

EngineeringThin Film Process TechnologySilicon On InsulatorInterconnect (Integrated Circuits)Semiconductor Device +15