Concepedia

Y. S. Kim

YS

5

Publications

109

Citations

5

H-Index

1999

Active since

Affiliations

Tokyo Institute of Technology(Current)

Fujitsu (Japan)

Dai Nippon Printing (Japan)

Industrial Technology Research Institute

Y. S. Kim is an author at Tokyo Institute of Technology specializing in microelectronics, engineering, and electronic packaging.

Top concepts

EngineeringMicroelectronicsApplied PhysicsElectronic PackagingElectrical EngineeringMicrofabricationThin FilmsMicrostructureMaterial ScienceIntegrated Circuits

Publications per year

1999–2018

5

Publications

5

Ultra thinning down to 4-&#x00B5;m using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications

Y. S. Kim, Shuhei Kodama, Y. Mizushima et al. · 2014 · 33 citations

Engineering, Emerging Memory Technology, Integrated Circuits +21

Assessing merged DRAM/Logic technology

Y. S. Kim, Tom W. Chen · Integration · 1999 · 28 citations

Hardware Security, Engineering, Computer Design +5

A robust wafer thinning down to 2.6-μm for bumpless interconnects and DRAM WOW applications

Y. S. Kim, Shuhei Kodama, Y. Mizushima et al. · 2015 · 19 citations

Engineering, Thin Film Process Technology, Interconnect (Integrated Circuits) +18

Optimization of Via Bottom Cleaning for Bumpless Interconnects and Wafer-on-Wafer (WOW) Integration

Y. S. Kim, Shuhei Kodama, Y. Mizushima et al. · 2018 · 18 citations

Engineering, Dry Process, Integrated Circuits +18

Electrical characteristics of bumpless interconnects for through silicon via (TSV) and Wafer-On-Wafer (WOW) integration

Y. S. Kim, Shuhei Kodama, Noritoshi Maeda et al. · 2016 · 11 citations

Engineering, Device Integration, Interconnect (Integrated Circuits) +17

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