Optimization of Via Bottom Cleaning for Bumpless Interconnects and Wafer-on-Wafer (WOW) Integration

Abstract

Effect of via bottom cleaning process and electrical characteristics of through-silicon via (TSV) are investigated using 300-mm wafer-on-wafer (WOW) process. Several kinds of cleaning method including wet and dry process were employed after TSV and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> liner etching process. It was found that sequential O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma and Ar sputtering provides the lowest resistance and the smallest variation among the conditions we have evaluated, which is 0.3 times lower resistance than that of the reference. The cleaning treatments were especially effective to clean the outer region of wafer, so that significant improvement of uniformity was achieved. However, O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma and Ar sputtering increase the leakage current due to redeposited copper during the plasma treatments. A lower TSV resistance with excellent uniformity can be helpful to design high band width and lower power consumption device due to its lower impedance characteristics.