Electrical characteristics of bumpless interconnects for through silicon via (TSV) and Wafer-On-Wafer (WOW) integration

Abstract

This paper describes electrical characteristics of bumpless and dual-damascene TSV interconnects for three-dimensional integration (3DI) using Wafer-on-Wafer (WOW) technology. Process optimization counter to integration issues of TSV formation process is demonstrated using test vehicle fabricated with 300-mm wafer and characterized by chain resistance and leakage current in the wafer level.