Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

Abstract

Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along the sidewall, so-called scalloping, formed by Bosch etching, are strongly related to leakage currents between adjacent TSVs. Microcracks in the SiON barriers were observed by TEM analysis and correlated with the sidewall roughness. FEM simulations of the stress concentration along the sidewall roughness clarified the origin of cracking. A non-Bosch etching process showed smooth sidewall surface and we consider it to be feasible for reliable TSV interconnects.