C. Vizioz

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Sylvain Barraud, V. Lapras, B. Prévitali et al. · 2017 · 147 citations · Full text

Electrical Engineering, Gate-all-around Stacked-nanowires Fets, Engineering +10

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

Sylvain Barraud, R. Coquand, M. Cassé et al. · IEEE Electron Device Letters · 2012 · 145 citations

Electrical Engineering, Semiconductor Device, Engineering +11

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, T. Poiroux, J. Widiez et al. · IEEE Electron Device Letters · 2005 · 128 citations

Alignment Marks, Electrical Engineering, Engineering +7

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

C. Dupré, A. Hubert, Stéphane Bécu et al. · 2008 · 111 citations

Co-processed Finfet, Engineering, Integrated Circuits +17

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Sylvain Barraud, V. Lapras, Marie-Pierre Samson et al. · 2016 · 108 citations · Full text

Engineering, Inner Spacer, Integrated Circuits +16