K. Maitra

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Hikaru Kawasaki, V. Basker, T. Yamashita et al. · 2009 · 94 citations

Engineering, Computer Engineering, Electrical Engineering +17

Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

A. Kerber, K. Maitra, Amlan Majumdar et al. · IEEE Transactions on Electron Devices · 2008 · 79 citations

Engineering, Computer Engineering, Electrical Engineering +11

Cascaded Switching Networks of Two-Input Flexible Cells

K. Maitra · IEEE Transactions on Electronic Computers · 1962 · 66 citations

Computing, Computer Engineering, Computer Science +13

A 0.063 µm<sup>2</sup> FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

V. Basker, T. Standaert, Hikaru Kawasaki et al. · 2010 · 60 citations

Engineering, Computer Engineering, Electrical Engineering +11

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

Vijay Narayanan, K. Maitra, B.P. Linder et al. · IEEE Electron Device Letters · 2006 · 46 citations

Engineering, Electrical Engineering, Materials Science +17