Vertical Ferroelectric HfO<inf>2</inf> FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory

Karine Florent, Milan Pešić, A. Subirats, +10

Non-volatile MemoryEngineeringEmerging Memory TechnologyFerroelectric Random-access Memory3D Memory +15

Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells

Elisa Vianello, F. Driussi, A. Arreghini, +6

IEEE Transactions on Electron Devices

Non-volatile MemoryEngineeringVlsi DesignSin LayerEmerging Memory Technology +21

Long term charge retention dynamics of SONOS cells

A. Arreghini, N. Akil, F. Driussi, +3

Solid-State Electronics

EngineeringCell DivisionElectrophysiologyCell BiologySonos Cells +7

Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices

Alessandro Maconi, A. Arreghini, Christian Monzio Compagnoni, +4

Solid-State Electronics

Electrical EngineeringSemiconductor DeviceEngineeringAdvanced Packaging (Semiconductors)Nanoelectronics +7

Experimental Characterization of the Vertical Position of the Trapped Charge in Si Nitride-Based Nonvolatile Memory Cells

A. Arreghini, F. Driussi, Elisa Vianello, +5

IEEE Transactions on Electron Devices

Vertical PositionNon-volatile MemoryEngineeringEmerging Memory TechnologyPhase Change Memory +15

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

G. Van den bosch, Gouri Sankar Kar, Pieter Blomme, +11

IEEE Electron Device Letters

Non-volatile MemoryEngineeringEmerging Memory TechnologyIntegrated Circuits3D Memory +14

Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories

A. Suhane, A. Arreghini, R. Degraeve, +6

IEEE Electron Device Letters

Trap DistributionNon-volatile MemoryEngineeringCharge TransportSemiconductor Device +17

A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations

Andrea Padovani, A. Arreghini, Luca Vandelli, +4

IEEE Transactions on Electron Devices

Non-volatile MemoryElectrical EngineeringErase OperationEngineeringPhysics +9

Statistical poly-Si grain boundary model with discrete charging defects and its 2D and 3D implementation for vertical 3D NAND channels

R. Degraeve, Sergiu Clima, V. Putcha, +12

EngineeringVertical Nand DevicesDefect ToleranceSemiconductor DeviceNanoelectronics +16

Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories

M. Toledano-Luque, R. Degraeve, B. Kaczer, +10

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureIntegrated Circuits +17