Concepedia

Surface Passivation of Ge MOS Devices by ${\rm SmGeO}_{\bf{x}}$ With Sub-nm EOT

Chia-Chun Lin, Yung‐Hsien Wu, Chaoyi Wu, Ching-Wei Lee

IEEE Electron Device Letters · 2014 · 18 citations · 16 references

Abstract

Ge MOS devices passivated by SmGeO x with equivalent oxide thickness of 0.61 nm were employed as the platform to evaluate the eligibility of SmGeO x as Ge surface passivation layer. The SmGeO x layer was formed by deposition of Sm 2 O 3 on Ge substrate with a subsequent O 2 annealing and the formation of SmGeOx was confirmed by X-ray photoelectron spectroscopy. The tiny frequency dispersion in capacitance measurement and a low interface trap density of 5.1×10 11 cm -2 eV -1 near midgap attest to desirable passivation effect and it can be ascribed to Sm-Ge-O bonding, which is favorable in mitigating dangling bonds at Ge surface. In addition, the small hysteresis in capacitance also suggests good quality of bulk dielectric. Due to the small amount of bulk traps and large conduction band offset with respect to Ge, it enjoys low leakage current of 0.36 A/cm 2 at gate bias of V fb (flatband voltage)-1 V. Through the test of bias temperature instability, the passivation layer demonstrates reasonable reliability performance in terms of 65-mV flatband voltage shift at 85 ° C after stressing with -16 MV/cm for 1000 s. With these characteristics, SmGeO x is promising as a passivation layer for aggressively scaled Ge MOS devices.