A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging

Abstract

Advances in packaging technologies have accelerated heterogenous disaggregation of SoCs by enabling the integration of IPs in different technology nodes within a single package. Such systems-in-package (SiP) require highly bandwidth-efficient, low-power die-to-die (D2D) links with low latency and BER. The Universal Chiplet Interconnect Express (UCle) standard [1] offers a blueprint on building D2D links that provide solutions to these challenges. Recently, proprietary D2D links for 2.5D interposers have been published [2]–[7]. However, such custom solutions limit interoperability across different vendors, which UCle standard enables. This work demonstrates a 4-to-16Gb/s/pin UCle-compliant link, implemented in a 2.5D CoWoS-S package.