IEEE Electron Device Letters · 2021 · 27 citations · 26 references
Materials ScienceSemiconductorsElectrical EngineeringPolarity GateEngineeringElectronic MaterialsFerroelectric ApplicationSemiconductor TechnologyNanotechnologyNanoelectronicsApplied PhysicsFerroelectric MaterialsSemiconductor MaterialElectrostatic DopingPyroelectricityFe-ed NsfetsSemiconductor DeviceSemiconductor Nanostructures
A ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing non-volatile and programmable free electrons and holes for nanoscale devices. We show that Fe-ED achieves non-volatility and reconfigurability via the ferroelectric film inserted into the polarity gate, producing the reconfigurable nanosheet FETs (NSFETs) without the requirement of a constant bias. Thanks to the naturally formed lightly doped drain structures and the extremely high doping concentration over 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> in source/drain (S/D) regions, Fe-ED NSFETs exhibit the promising potential benefits for device scaling including the improved subthreshold swing, the suppressed drain-induced barrier lowering, and the ultralow S/D region resistance. Our study suggests a promising doping strategy of Fe-ED for versatile reconfigurable nanoscale transistors and highly integrated circuits.
26
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
N. Loubet, Terence B. Hook, P. Montanini et al. · 2017 · 939 citations
Reconfigurable Silicon Nanowire Transistors
André Heinzig, Stefan Slesazeck, Franz Kreupl et al. · Nano Letters · 2011 · 432 citations · Full text