IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2019 · 69 citations · 28 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingFault-tolerant SystemsMicroelectronicsDevice ReliabilityHardware Fault ToleranceIntegrated Circuit DesignIntegrated Circuit FabricationReliable System DesignSemiconductor ReliabilityFault-tolerant ArchitectureHardware Overhead AnalysisSiliconThree-dimensional IntegrationThrough-silicon Via DesignThrough-silicon ViasVlsi ImplementationYield Enhancement
Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.
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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Uksong Kang, Hoeju Chung, Seongmoo Heo et al. · IEEE Journal of Solid-State Circuits · 2010 · 487 citations
Engineering, Computer Engineering, Electrical Engineering +15
Beyond the flow decomposition barrier
Andrew V. Goldberg, Satish Rao · Journal of the ACM · 1998 · 474 citations · Full text
TSV redundancy: Architecture and design issues in 3D IC
Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang et al. · 2010 · 150 citations
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Igor Loi, Subhasish Mitra, Thomas H. Lee et al. · 2008 · 146 citations
Engineering, Computer Engineering, Electrical Engineering +17