Hardware Overhead Analysis
Hardware Overhead Analysis is a systematic evaluation method used in logic locking research to quantify the additional resource consumption, performance degradation, or power dissipation introduced by security-oriented modifications in integrated circuits.
555
Publications
18.6K
Citations
1.3K
Authors
430
Institutions
Publications per year
2017–2026
104
Parents
555
A Case for MLP-Aware Cache Replacement
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu et al. · ACM SIGARCH Computer Architecture News · 2006 · 272 citations
A Case for MLP-Aware Cache Replacement
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu et al. · 2006 · 205 citations
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430
Stanford University
Stanford, United States
13 h-index
43 publications
4.1K citations
Princeton University
Princeton, United States
13 h-index
31 publications
929 citations
The University of Texas at Austin
Austin, United States
12 h-index
32 publications
2.7K citations
Yonsei University
Seoul, South Korea
11 h-index
39 publications
942 citations
University of Stuttgart
Stuttgart, Germany
10 h-index
21 publications
1.2K citations
Case Western Reserve University
Cleveland, United States
10 h-index
23 publications
672 citations
University of Southern California
Los Angeles, United States
10 h-index
19 publications
674 citations

University of Minnesota
Minneapolis, United States
10 h-index
28 publications
980 citations
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42 publications · 1.7K citations
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31 publications · 1.2K citations
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27 publications · 921 citations
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7 publications · 163 citations
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7 publications · 181 citations
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