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Gate Reliability of p-GaN HEMT With Gate Metal Retraction

54

Citations

21

References

2019

Year

Abstract

In this article, we present an analysis of the gate degradation induced by long-term forward gate stress in GaN-based power HEMTs with p-type gate, controlled by a Schottky metal-retracted/p-GaN junction. In particular, time-dependent gate breakdown and threshold voltage instability are investigated as function of different geometries, gate biases, and temperatures. The introduction of a gate metal retraction (GMR) process step improves the device lifetime because it suppresses the onset of the leakage current flow occurring at the gate edges for relatively high gate voltage. However, biasing GMR p-GaN HEMT at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> > 8 V and T > 80 °C, a new degradation mechanism shows up, possibly altering the lifetime even at low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> operation. Main results in this article demonstrate that although at high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and high T, a localized degradation effect ascribed to the device isolation region is responsible for time-dependent gate breakdown, thanks to GMR higher operating voltages compatible with ten-year continuous operation is attained. Finally, the longer device lifetime at moderate V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> values brought by GMR allows evaluating the threshold voltage instability for long stress times (≈112 h) at relatively high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and high T, leading to the observation of a saturation of the long-term positive threshold voltage shift and providing additional information about the underlying physical degradation mechanisms. Overall, the saturated 0.65-V AVTH under worst-case condition (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 7 V at 150 °C, i.e., correspondingto ten-year lifetime) reveals a reliable and fairly stable technology with respect to forward gate stress.

References

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