Standard wafer with programed defects to evaluate the pattern inspection tools for 300-mm wafer fabrication for 7-nm node and beyond

Abstract

Background: Standard patterned sample with programed defects (PDs) is effective to evaluate the tool performance of pattern inspection system, but the fabrication of such standard sample, having large area dense patterns with PDs suitable for the evaluation of sub-7-nm node, is difficult. Aim: The goal of this study is to fabricate a standard sample to evaluate the performance of inspection tool for below 7-nm nodes. Approach: We use electron beam lithography with an acceleration voltage of 130 keV to fabricate standard sample. Results: We form large area dense sub-16-nm half pitch (hp) line and space (LS) patterns with PDs on 300-mm-Si-wafers, and 10- to 7-nm hp LS patterns on a 100-mm-Si wafer. Approximately 5-nm PDs with shapes including protrusions, intrusions, bridges, and openings are formed without additional defects. Moreover, pattern-etched Si wafers with 16- to 12-nm hp LS are successfully fabricated. A 100-mm-wafer with patterns is mounted into a 300-mm-Si wafer. Conclusions: The acceleration voltage of 130 keV is sufficient for the fabrication of large area dense pattern with PDs suitable for the evaluation of sub-7-nm node. Moreover, the fabricated standard wafers are useful to evaluate the tool performance of the inspection system for 300-mm wafer fabrication.