Study of Annular Copper-Filled TSVs of Sensor and Interposer Chips for 3-D Integration

Abstract

Actually, the 3-D integrating process is often viewed as the integration of wafer thinning, through-silicon vias (TSVs) etching and filling, redistribution layer formulation, and microbump bonding. The TSV formulation is a critical process because TSV decides the quality of the interconnection. In this paper, the annular copper-filled TSVs are fabricated into the sensor and interposer chips, which are thinned to 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> , and 10- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -diameter TSV is etched and annularly filled by 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick copper only utilizing sputtering. It can significantly simplify the chip fabricating process, which only includes the TSV etching (deep reactive-ion etching), insulating layer formation, barrier layer sputtering and copper layer sputtering, and peeling. The thermal reliability of the annularly filled TSV structure is studied by the finite-element simulation, and it is found that the thermal stress is markedly reduced, and in the thermal cycle test, annularly filled TSV samples show better reliability. Meanwhile, the measured electrical conductivity shows a slightly worse but enough electrical conductivity property.