Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Abstract

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.