L.T. Su - Concepedia

Concepedia

Author

L.T. Su

Massachusetts Institute of Technology

Also Known As

L. Su, L. T. Su, L.T. Su, Lehui Su, Li-Tong Su, LiJie Su, Lichen Su, Linli Su

41

Publications

1.7K

Citations

21

H-Index

47

Concepts

All Affiliations

Massachusetts Institute of Technology IBM (United States)Digital Wave (United States)Texas Instruments (United States)Advanced Micro Devices (United States)

LS

About

L.T. Su is an author at Massachusetts Institute of Technology specializing in electrical engineering, engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	21	27	1.7K
2	Electrical Engineering	21	26	1.7K
3	Applied Physics	15	18	1.1K
4	Computer Engineering	10	10	348
5	Computer Science	1	1	12

L.T. Su

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27

Publications

1.7K

Citations

21

H-Index

	Year	Citations
Full copper wiring in a sub-0.25 μm CMOS ULSI technology D. Edelstein, J. Heidenreich, R. Goldblatt, 3D Ic ArchitectureElectrical EngineeringCu WiringFull Copper WiringEngineering	2002	350
Measurement and modeling of self-heating in SOI nMOSFET's L.T. Su, J.E. Chung, D.A. Antoniadis, IEEE Transactions on Electron Devices Device ModelingSoi NmosfetElectrical EngineeringSoi Device DesignEngineering	1994	329
Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's L.T. Su, J.B. Jacobs, J.E. Chung, IEEE Electron Device Letters Device ModelingElectrical EngineeringDeep-submicrometer Channel DesignVlsi DesignDeep-submicrometer Soi Mosfet	1994	94
Annealing-temperature dependence of the thermal conductivity of LPCVD silicon-dioxide layers Kenneth E. Goodson, M. I. Flik, L.T. Su, IEEE Electron Device Letters Materials ScienceElectrical EngineeringElectronic CircuitsEngineeringSilicon On Insulator	1993	92
Prediction and Measurement of the Thermal Conductivity of Amorphous Dielectric Layers Kenneth E. Goodson, M. I. Flik, L.T. Su, Journal of Heat Transfer EngineeringBulk ConductivitySilicon On InsulatorThermal ConductivityThermodynamics	1994	85
A 480-MHz RISC microprocessor in a 0.12-μm L/sub eff/ CMOS technology with copper interconnects C. Akrout, Jörg Bialas, M. Canada, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsProcessor Architecture	1998	65
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E. Leobandung, H. Nayakama, D. Mocuta, Electrical EngineeringEngineeringVlsi DesignAdvanced Packaging (Semiconductors)Nm Soi Technology	2005	65
A study of deep-submicron MOSFET scaling based on experiment and simulation Hang Hu, J.B. Jacobs, L.T. Su, IEEE Transactions on Electron Devices Device ModelingScaling RelationshipsElectrical EngineeringSemiconductor DeviceEngineering	1995	62
SOI MOSFET effective channel mobility M. Sherony, L.T. Su, J.E. Chung, IEEE Transactions on Electron Devices Device ModelingSemiconductor TechnologyElectrical EngineeringEffective Electric FieldEngineering	1994	61
Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's L.T. Su, J.B. Jacobs, J.E. Chung, IEEE Electron Device Letters Device ModelingElectrical EngineeringDeep-submicrometer Channel DesignVlsi DesignDeep-submicrometer Soi Mosfet	1994	48

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