Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Abstract

The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the thermal cycling test is also performed.