Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

John H. Lau, Ming Li, Dewen Tian, +19

IEEE Transactions on Components Packaging and Manufacturing Technology

Electrical EngineeringChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)Wafer Scale Processing +13

Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

John H. Lau, Ming Li, Qingqian Margie Li, +23

IEEE Transactions on Components Packaging and Manufacturing Technology

Advanced PackagingElectrical EngineeringChip-scale PackageEngineeringCompression Molding +13

Fan-Out Wafer-Level Packaging for Heterogeneous Integration

John H. Lau, Ming Li, Margie Li Qingqian, +25

IEEE Transactions on Components Packaging and Manufacturing Technology

3D Ic ArchitectureElectrical EngineeringNew Assembly ProcessEngineeringChip-scale Package +13

Effects of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die

Neil Mclellan, Nelson Fan, Shilai Liu, +2

Journal of Electronic Packaging

EngineeringMechanical EngineeringWafer Thinning ConditionSilicon On InsulatorSurface Processing +17

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Cheng-Ta Ko, John H. Lau, Ming Li, +29

IEEE Transactions on Components Packaging and Manufacturing Technology

EngineeringEnergy EfficiencyComputer ArchitectureInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors) +14

Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers

John H. Lau, Ming Li, Lei Yang, +16

IEEE Transactions on Components Packaging and Manufacturing Technology

EngineeringMechanical EngineeringFowlp FabricationIntegrated CircuitsWafer Scale Processing +17

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

John H. Lau, Ming Li, Dewen Tian, +16

Electrical EngineeringChip SizeEngineeringChip-scale PackageAdvanced Packaging (Semiconductors) +13

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

John H. Lau, Ming Li, Nelson Fan, +23

Journal of Microelectronics and Electronic Packaging

EngineeringComputer ArchitectureWafer Scale ProcessingAdvanced Packaging (Semiconductors)Materials Fabrication +15

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Cheng-Ta Ko, Chieh-Lin Chang, Jhih-Yuan Pan, +30

EngineeringEnergy EfficiencyComputer ArchitectureAdvanced Packaging (Semiconductors)Heterogeneous Integration +16

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Cheng-Ta Ko, Henry Yang, John H. Lau, +24

Journal of Microelectronics and Electronic Packaging

Materials ScienceAdvanced PackagingElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors) +13