Extreme wafer thinning optimization for via-last applications

Abstract

As the 3D interconnect density is increasing exponentially when scaling to lower levels of the interconnect wiring, we see that very soon 3D interconnect pitches of 5 μm and below will be required. Current 3D-SIC (3D-Stacked IC) technologies do not yet offer such interconnect densities and it is expected that most of the 3D-SOC (3D System On Chip) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach. The wafer thinning process becomes very critical when final Si thicknesses of the top wafer in the 5μm range or below are considered. Indeed, a good control of the final Si thickness as well as the total thickness variation (TTV) are necessary to enable a stable via-last etch process with minimum undercut (notching). Two extreme wafer thinning approaches are investigated and compared in terms of process performance and cost of ownership.