Patterning control strategies for minimum edge placement error in logic devices

TLDR

Multi‑patterning semiconductor manufacturing introduces edge placement errors from successive lithography and etching steps that shape the final pattern contour. This study investigates edge placement error in multi‑patterning and proposes a holistic optimization strategy to reduce it. Using IMEC’s 7‑nm logic device flow with Self‑Aligned‑Quadruple‑Patterning, the authors quantify EPE via angle‑resolved scatterometry, apply scanner actuator control for high‑order overlay corrections, and employ computational lithography to minimize imaging‑induced placement errors. The analysis shows that ArF‑to‑EUV overlay, CDU, and local CD/placement errors dominate EPE, and the authors devise step‑specific and final‑pattern optimization strategies to mitigate them.

Abstract

In this paper we discuss the edge placement error (EPE) for multi-patterning semiconductor manufacturing. In a multi-patterning scheme the creation of the final pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. We describe the fidelity of the final pattern in terms of EPE, which is defined as the relative displacement of the edges of two features from their intended target position. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As an experimental test vehicle we use the 7-nm logic device patterning process flow as developed by IMEC. This patterning process is based on Self-Aligned-Quadruple-Patterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography. The computational metrology method to determine EPE is explained. It will be shown that ArF to EUV overlay, CDU from the individual process steps, and local CD and placement of the individual pattern features, are the important contributors. Based on the error budget, we developed an optimization strategy for each individual step and for the final pattern. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets.