Edge Placement Error
Edge Placement Error is a metric in mask design that quantifies the deviation between the intended position of a feature edge on a photomask and its actual fabricated position, serving to assess the precision of pattern transfer in semiconductor lithography.
70
Publications
1.8K
Citations
243
Authors
57
Institutions
Publications per year
2017–2026
22
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Epe
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Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography
Jan Mulkens, M. M. Hanna, Hannah Wei et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2015 · 68 citations
Engineering, Electrical Engineering, Manufacturing Engineering +17
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University of Illinois Urbana-Champaign, United States
4 publications · 69 citations
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4
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1–5 of 243
57
The University of Texas at Austin
Austin, United States
11 h-index
27 publications
818 citations
ASML (Netherlands)
Veldhoven, The Netherlands
9 h-index
44 publications
1.5K citations
Mentor Technologies
Tulsa, United States
6 h-index
12 publications
292 citations
University of California San Diego
San Diego, United States
5 h-index
12 publications
208 citations
University of Illinois Urbana-Champaign
Urbana, United States
4 h-index
10 publications
176 citations
IMEC
Leuven, Belgium
4 h-index
14 publications
176 citations
Hitachi (Japan)
Tokyo, Japan
4 h-index
10 publications
206 citations
BlazeTech (United States)
Woburn, United States
4 h-index
7 publications
115 citations
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20 publications · 495 citations
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5 publications · 141 citations
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5 publications · 108 citations
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Conference · 2 publications · 33 citations
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1 publications · 18 citations
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