A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Abstract

In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on a complementary switched injection technique and a sub-sampling bang-bang detector (SSBBPD) is presented. The proposed PLL does not require a timing calibration circuit for phase alignment between the PLL and injection loops. Moreover, instead of a pulse generator, a complementary switched injection technique is used to achieve high frequency (e.g. 5 GHz) injection-locked oscillator. The proposed PLL was implemented in a 65-nm CMOS process on an active area of 0.06mm2, with measurement result showing that it achieves a 484-fs integrated RMS jitter from 1 kHz to 40 MHz at a 5-GHz output frequency while consuming 15.4 mW.