Han-Gon Ko

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels

Han-Gon Ko, Soyeong Shin, Jonghyun Oh et al. · 2020 · 36 citations

3D Ic Architecture, Electrical Engineering, Silicon Interposer +15

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler

Moon‐Chul Choi, Han-Gon Ko, Jonghyun Oh et al. · 2020 · 35 citations

Engineering, Measurement, Analog Design +17

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS

Kwanseo Park, Minkyo Shim, Han-Gon Ko et al. · 2020 · 27 citations

Continuous-rate Referenceless Clock, Engineering, Machine Learning +8

A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Sung‐Yong Cho, Sungwoo Kim, Min-Seong Choo et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 26 citations

Electrical Engineering, High-frequency Device, Clock Recovery +5

Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector

Kwanseo Park, Minkyo Shim, Han-Gon Ko et al. · IEEE Journal of Solid-State Circuits · 2021 · 26 citations

Electrical Engineering, Cdr Circuit, Engineering +13