Publication | Closed Access
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler
35
Citations
0
References
2020
Year
Unknown Venue
EngineeringMeasurementAnalog DesignComputer ArchitectureEducationWeight-adjusting Mm CdrIntegrated CircuitsImage SensorClock RecoveryCalibrationMixed-signal Integrated CircuitInstrumentationAdaptive DfeAnalog-to-digital ConverterComputer EngineeringPower ConsumptionSignal ProcessingEye TrackingAdaptive Decision-feedback EqualizerDigital Circuit Design
This paper presents a forwarded-clock receiver (RX) that consists of a weight-adjusting sign-sign Mueller-Müller clock and data recovery (CDR) and an adaptive decision-feedback equalizer (DFE) with a single shared error sampler. Only two samples per bit are utilized for both CDR and adaptive DFE, which minimizes clocking power consumption. In addition, a maximum-eye tracking algorithm is proposed to enhance the vertical eye margin without any extra high-speed analog circuitry. The RX fabricated in a 28nm CMOS technology achieves BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> with a 20dB-loss channel. It occupies an active area of 0.108 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consumes 56.65 mW at 28 Gb/s.