Deog‐Kyoon Jeong - Concepedia

Author

Deog‐Kyoon Jeong

Also Known As

D. Jeong, D.-K. Jeong, D.K. Jeong, Deog-Kyoon Jeong, Deog-kyoon Jeong, Deog‐Kyoon Jeong, Dongmin Jeong, Jeong, Jeong, D., Jeong, Dawoon

373

Publications

5.2K

Citations

H-Index

102

Concepts

All Affiliations

Seoul National University SK Group (South Korea)Samsung (South Korea)Silicon Labs (United States)University of California, Berkeley

About

Deog‐Kyoon Jeong is an author at Seoul National University specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	34	107	3.5K
2	Computer Engineering	34	100	3.4K
3	Education	1	1	35
4	Language Studies	1	1	21
5	Natural Sciences	1	1	12

Deog‐Kyoon Jeong

145

Publications

4.6K

Citations

H-Index

Page 1

	Year	Citations
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance Yongsam Moon, Jongsang Choi, Kyeongho Lee, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignClock RecoveryJitter Supply SensitivityMixed-signal Integrated Circuit	2000	186
Design of PLL-based clock generation circuits Deog‐Kyoon Jeong, G. Borriello, D.A. Hodges, IEEE Journal of Solid-State Circuits Electrical EngineeringClock PhasesInternal Clock SignalsVlsi DesignEngineering	1987	136
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL Sungjoon Kim, Kyeongho Lee, Yongsam Moon, IEEE Journal of Solid-State Circuits System On ChipEngineeringVlsi DesignClock RecoveryData Converter	1997	117
A 0.18-&lt;tex&gt;$muhboxm$&lt;/tex&gt;CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method Jae‐Woong Choi, MinHo Hwang, Deog‐Kyoon Jeong IEEE Journal of Solid-State Circuits Mixed-signal Integrated CircuitAnalog DesignPrototype ChipChannel EqualizationComputer Engineering	2004	116
Reduction of pump current mismatch in charge-pump PLL MinHo Hwang, Jongwook Kim, Deog‐Kyoon Jeong Electronics Letters Pll DynamicsElectrical EngineeringEngineeringDual Compensation CircuitsPump Current Mismatch	2009	103
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems Yido Koo, Hyungki Huh, Yong-Sik Cho, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringFractional SpursProposed Frequency SynthesizerEngineering	2002	90
A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems Jiho Han, Deog‐Kyoon Jeong IEEE Transactions on Instrumentation and Measurement Time-sensitive NetworkingIeee 1588EngineeringMeasurementTime Synchronization	2009	81
A Single-Inductor, Multiple-Channel Current-Balancing LED Driver for Display Backlight Applications Hyun‐Chang Kim, Chang Soo Yoon, Deog‐Kyoon Jeong, IEEE Transactions on Industry Applications Electrical EngineeringSolid-state LightingPrototype Led DriverEngineeringDisplay Backlight Applications	2014	77
A CMOS serial link for fully duplexed data communication Kyeongho Lee, Sungjoon Kim, Gijung Ahn, IEEE Journal of Solid-State Circuits Serialization LanguageEngineeringMultiplexingFull DuplexClock Recovery	1995	76
Multi-gigabit-rate clock and data recovery based on blind oversampling Jaeha Kim, Deog‐Kyoon Jeong IEEE Communications Magazine Jitter TolerancesJitter Tolerance SpecificationsEngineeringMeasurementJitter Tolerance	2003	74

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