Deog‐Kyoon Jeong

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

Yongsam Moon, Jongsang Choi, Kyeongho Lee et al. · IEEE Journal of Solid-State Circuits · 2000 · 186 citations

Engineering, Vlsi Design, Clock Recovery +11

Design of PLL-based clock generation circuits

Deog‐Kyoon Jeong, G. Borriello, D.A. Hodges et al. · IEEE Journal of Solid-State Circuits · 1987 · 136 citations

Electrical Engineering, Clock Phases, Internal Clock Signals +10

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Sungjoon Kim, Kyeongho Lee, Yongsam Moon et al. · IEEE Journal of Solid-State Circuits · 1997 · 117 citations

System On Chip, Engineering, Vlsi Design +11

A 0.18-<tex>$muhboxm$</tex>CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method

Jae‐Woong Choi, MinHo Hwang, Deog‐Kyoon Jeong · IEEE Journal of Solid-State Circuits · 2004 · 116 citations

Mixed-signal Integrated Circuit, Analog Design, Prototype Chip +7

Reduction of pump current mismatch in charge-pump PLL

MinHo Hwang, Jongwook Kim, Deog‐Kyoon Jeong · Electronics Letters · 2009 · 103 citations

Pll Dynamics, Electrical Engineering, Engineering +5