A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

Abstract

This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the effect of supply noise. Measured results show peak-to-peak jitter of 150 ps and r.m.s. jitter of 15.7 ps on the clock line. Two experimental chips with 4-pin interface have been fabricated with a 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mb/s per pin.