Kwanseo Park - Concepedia

Author

Kwanseo Park

Seoul National University ORCID

Also Known As

Kwanseo Park

Publications

627

Citations

H-Index

Concepts

All Affiliations

Seoul National University University of California, Berkeley SK Group (South Korea)Samsung (South Korea)Yonsei University

About

Kwanseo Park is an author at Seoul National University specializing in computer engineering, engineering, and signal processing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	14	14	458
2	Engineering	13	13	413
3	Electrical Engineering	5	5	138
4	Systems Engineering	2	2	68
5	Asynchronous Circuits	1	1	20

Kwanseo Park

Publications

532

Citations

H-Index

Page 1

	Year	Citations
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS Woorham Bae, Haram Ju, Kwanseo Park, IEEE Journal of Solid-State Circuits Two-stage Ring OscillatorEngineeringRadio FrequencyOscillatorsHigh-frequency Device	2016	59
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference Jinhyung Lee, Kwang‐Ho Lee, Hyo‐Jun Kim, IEEE Journal of Solid-State Circuits Digital Multimedia BroadcastingAdaptive FilterEngineeringVideo Coding FormatData-level Reference	2020	52
A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS Kwanseo Park, Woorham Bae, Jinhyung Lee, IEEE Journal of Solid-State Circuits Oversampling PfdEngineeringClock RecoveryData ConverterMixed-signal Integrated Circuit	2018	46
A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS Kwanseo Park, Kwang‐Ho Lee, Sung‐Yong Cho, IEEE Journal of Solid-State Circuits Continuous-rate Referenceless ClockPrototype Cdr CircuitCdr CircuitHigh-frequency DeviceClock Recovery	2020	45
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, IEEE Journal of Solid-State Circuits Electrical EngineeringBerkeley Analog GeneratorEngineeringVlsi DesignAnalog-to-digital Converter	2021	40
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels Han-Gon Ko, Soyeong Shin, Jonghyun Oh, 3D Ic ArchitectureElectrical EngineeringSilicon InterposerEngineeringVlsi Design	2020	36
8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS Minsoo Choi, Zhongkai Wang, Kyoungtae Lee, Pam-4 100Gb/sVlsi DesignEngineeringNrz TransmitterComputer Engineering	2021	34
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS Kwanseo Park, Minkyo Shim, Han-Gon Ko, Continuous-rate Referenceless ClockEngineeringMachine LearningReferenceless CdrClock Recovery	2020	27
Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector Kwanseo Park, Minkyo Shim, Han-Gon Ko, IEEE Journal of Solid-State Circuits Electrical EngineeringCdr CircuitEngineeringDesign TechniquesClock Recovery	2021	26
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Photonics3-Tap Asymmetric FfeEngineeringHigh-speed Pam-4 SignalingMixed-signal Integrated Circuit	2019	21

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