IEEE Journal of Solid-State Circuits · 2021 · 45 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignClock Distribution NetworksClock ManagementCmos Circuit DesignConfigurable Logic BlocksMixed-signal Integrated Circuit DesignMixed-signal IntegrationBandwidthClock DistributionClock Distribution DesignCmos Analog Circuit DesignInput/output Bandwidth OptimizationRf Cmos DesignTransceiver ArchitecturesTransceiver Design
This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.
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BAG2: A process-portable framework for generator-based AMS circuit design
Eric Chang, Jaeduk Han, Woorham Bae et al. · 2018 · 125 citations
Engineering, Computer Engineering, Electrical Engineering +17
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS
Jihwan Kim, Ajay Balankutty, Amr Elshazly et al. · 2015 · 102 citations