Clock Distribution Design is a method in digital integrated circuit design that ensures synchronized timing signals are delivered across a chip with minimal skew and jitter by strategically routing clock signals from a central source to all sequential elements.
227
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7.9K
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691
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178
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2017–2026
16
Publications
227
A clock distribution network for microprocessors
P.J. Restle, T. G. McNamara, Daniel Webber et al. · IEEE Journal of Solid-State Circuits · 2001 · 302 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 227
Authors
691
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1–5 of 691
Institutions
178
Intel (United States)
Santa Clara, United States
19 h-index
87 publications
6.4K citations
University of Rochester
Rochester, United States
16 h-index
43 publications
2.3K citations
IBM (United States)
Armonk, United States
12 h-index
48 publications
4.4K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
9 h-index
13 publications
1.2K citations
IBM Research - Austin
Austin, United States
9 h-index
34 publications
2.5K citations
Stanford University
Stanford, United States
6 h-index
19 publications
992 citations
Columbia University
New York, United States
6 h-index
9 publications
432 citations
University of Michigan
Ann Arbor, United States
6 h-index
7 publications
159 citations
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- IEEE Journal of Solid-State Circuits
32 publications · 2.4K citations
23
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
14 publications · 518 citations
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- IEEE Transactions on Applied Superconductivity
6 publications · 217 citations
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3 publications · 83 citations
3
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- Electronics Letters
3 publications · 33 citations
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