BAG: A designer-oriented integrated framework for the development of AMS circuit generators

TLDR

Such generators are parameterized design procedures that produce sized schematics and correct layouts optimized to meet a set of input specifications. We introduce BAG, the Berkeley Analog Generator, an integrated framework for developing generators of Analog and Mixed Signal (AMS) circuits. BAG integrates all design‑flow steps into one environment, offers schematic and layout helper classes, simplifies tasks such as technology characterization, testbench translation, simulator interfacing, physical verification, extraction, and parameterized layout creation, and has been used to design VCO and SC voltage regulator generators in a CMOS 65 nm process. This approach fosters design reuse, eases technology migration, shortens time‑to‑market, and remains close to the classical design flow, as demonstrated by automatic migration of our designs to a 40 nm process.

Abstract

We introduce BAG, the Berkeley Analog Generator, an integrated framework for the development of generators of Analog and Mixed Signal (AMS) circuits. Such generators are parameterized design procedures that produce sized schematics and correct layouts optimized to meet a set of input specifications. BAG extends previous work by implementing interfaces to integrate all steps of the design flow into a single environment and by providing helper classes - both at the schematic and layout level - to aid the designer in developing truly parameterized and technology-independent circuit generators. This simplifies the codification of common tasks including technology characterization, schematic and testbench translation, simulator interfacing, physical verification and extraction, and parameterized layout creation for common styles of layout. We believe that this approach will foster design reuse, ease technology migration, and shorten time-to-market, while remaining close to the classical design flow to ease adoption. We have used BAG to design generators for several circuits, including a Voltage Controlled Oscillator (VCO) and a Switched-Capacitor (SC) voltage regulator in a CMOS 65nm process. We also present results from automatic migration of our designs to a 40nm process.