Amr Elshazly

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Ahmed Elkholy, Tejasvi Anand, Woo‐Seok Choi et al. · IEEE Journal of Solid-State Circuits · 2015 · 126 citations

High Resolution Tdc, Data Converter, Mixed-signal Integrated Circuit +5

A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

Karthikeyan Reddy, Sachin Rao, Rajesh Inti et al. · IEEE Journal of Solid-State Circuits · 2012 · 115 citations

Second Stage, Engineering, Data Converter +11

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

Jihwan Kim, Ajay Balankutty, Amr Elshazly et al. · 2015 · 102 citations

Electrical Engineering, Engineering, Mixed-signal Integrated Circuit +10

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Amr Elshazly, Rajesh Inti, Ben Young et al. · IEEE Journal of Solid-State Circuits · 2013 · 90 citations

Hardware Security, Dpll Chips, Engineering +11

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques

Amr Elshazly, Sachin Rao, Brian Young et al. · IEEE Journal of Solid-State Circuits · 2014 · 80 citations

High Resolution, Engineering, Data Converter +10