Amr Elshazly - Concepedia

Author

Amr Elshazly

Intel (United States)ORCID

Also Known As

A. Elshazly, A.F.A. El-Shazly, Amr Elshazly

Publications

1.7K

Citations

H-Index

Concepts

All Affiliations

Intel (United States)Oregon State University University of Illinois Urbana-Champaign Indian Institute of Technology Madras Marvell (United States)

About

Amr Elshazly is an author at Intel (United States) specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	20	25	1.1K
2	Engineering	19	23	1.1K
3	Electrical Engineering	14	14	626
4	Computer Architecture	7	7	294
5	Embedded Systems	1	1	17

Amr Elshazly

Publications

1.6K

Citations

H-Index

Page 1

	Year	Citations
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC Ahmed Elkholy, Tejasvi Anand, Woo‐Seok Choi, IEEE Journal of Solid-State Circuits High Resolution TdcData ConverterMixed-signal Integrated CircuitAnalog DesignDigital Circuit Design	2015	126
A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer Karthikeyan Reddy, Sachin Rao, Rajesh Inti, IEEE Journal of Solid-State Circuits Second StageEngineeringData ConverterMixed-signal Integrated CircuitAnalog Design	2012	115
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS Jihwan Kim, Ajay Balankutty, Amr Elshazly, Electrical EngineeringEngineeringMixed-signal Integrated CircuitComputer EngineeringModulation Coding	2015	102
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops Amr Elshazly, Rajesh Inti, Ben Young, IEEE Journal of Solid-State Circuits Hardware SecurityDpll ChipsEngineeringAnalog-to-digital ConverterClock Recovery	2013	90
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques Amr Elshazly, Sachin Rao, Brian Young, IEEE Journal of Solid-State Circuits High ResolutionEngineeringData ConverterTdc LinearityAnalog Design	2014	80
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET Jihwan Kim, Ajay Balankutty, Rajeev Dokania, IEEE Journal of Solid-State Circuits Wireless CommunicationsEngineeringVlsi DesignGs/s TransmitterComputer Architecture	2018	79
A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, IEEE Journal of Solid-State Circuits Proposed Digital FnpllPhase Noise PerformanceClock RecoveryData ConverterMixed-signal Integrated Circuit	2016	77
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance Rajesh Inti, Wenjing Yin, Amr Elshazly, IEEE Journal of Solid-State Circuits Oscillator Clock PhasesClock RecoveryData ConverterMixed-signal Integrated CircuitAnalog Design	2011	76
High Frequency Buck Converter Design Using Time-Based Control Techniques Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringAnalog-to-digital ConverterData ConverterMixed-signal Integrated Circuit	2014	73
A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation Sachin Rao, Brian Young, Amr Elshazly, 2-Level Pwm ModulationData ConverterVco-based AdcAnalog DesignMixed-signal Integrated Circuit	2011	70

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