Ahmed Elkholy - Concepedia

Author

Ahmed Elkholy

University of Illinois Urbana-Champaign ORCID

Also Known As

A. El-Kholy, A. Elkholy, Ahmed El-Kholy, Ahmed Elkholy

Publications

Citations

H-Index

Concepts

All Affiliations

University of Illinois Urbana-Champaign Intel (United States)University of Illinois System Broadcom (United States)Indian Institute of Technology Madras

About

Ahmed Elkholy is an author at University of Illinois Urbana-Champaign specializing in engineering, computer engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	22	609
2	Computer Engineering	15	19	510
3	Electrical Engineering	13	15	439
4	Computer Architecture	4	4	103
5	Physics	1	1	11

Ahmed Elkholy

Publications

946

Citations

H-Index

Page 1

	Year	Citations
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC Ahmed Elkholy, Tejasvi Anand, Woo‐Seok Choi, IEEE Journal of Solid-State Circuits High Resolution TdcData ConverterMixed-signal Integrated CircuitAnalog DesignDigital Circuit Design	2015	126
A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, IEEE Journal of Solid-State Circuits Proposed Digital FnpllPhase Noise PerformanceClock RecoveryData ConverterMixed-signal Integrated Circuit	2016	77
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringHigh-frequency DeviceClock Recovery	2015	65
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, IEEE Journal of Solid-State Circuits Electrical EngineeringPhase Noise PerformanceClock MultiplierClock RecoveryData Converter	2015	53
A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS Mostafa G. Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, IEEE Journal of Solid-State Circuits PhotonicsLarge Feedback ResistanceEngineeringOptical Transmission SystemOptical Computing	2017	52
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringPrototype FdivHigh-frequency ClockData Converter	2018	51
A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringRadio FrequencyOscillatorsHigh-frequency Device	2019	49
8.6 A 2.5-to-5.75GHz 5mW 0.3ps<inf>rms</inf>-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, EngineeringVlsi DesignOscillatorsClock RecoveryTiming Analysis	2017	38
A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier Ahmed Elkholy, Ahmed Elmallah, Mostafa G. Ahmed, IEEE Journal of Solid-State Circuits EngineeringClock MultiplierVlsi DesignHigh-frequency DeviceClock Recovery	2018	37
A 0.0021 mm<sup>2</sup>1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, IEEE Journal of Solid-State Circuits Electrical EngineeringMw 2.2Vlsi DesignDigital PllsEngineering	2016	32

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