Romesh Kumar Nandwana

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana et al. · IEEE Journal of Solid-State Circuits · 2016 · 77 citations

Proposed Digital Fnpll, Phase Noise Performance, Clock Recovery +5

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/$\lambda$ PAM-4 Optical Links

K.R. Lakshmikumar, Alexander Kurylak, Manohar Nagaraju et al. · IEEE Journal of Solid-State Circuits · 2019 · 65 citations

Optical Materials, Engineering, Optical Transmission System +17

A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator

Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan et al. · IEEE Journal of Solid-State Circuits · 2015 · 59 citations

Passive Current Sharing, Electrical Engineering, Engineering +11

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena et al. · IEEE Journal of Solid-State Circuits · 2015 · 53 citations

Electrical Engineering, Phase Noise Performance, Clock Multiplier +5

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana et al. · IEEE Journal of Solid-State Circuits · 2019 · 49 citations

Electrical Engineering, Engineering, Radio Frequency +12