Rajesh Inti - Concepedia

Author

Rajesh Inti

Oregon State University ORCID

Also Known As

R. Inti, Rajesh Inti

Publications

856

Citations

H-Index

Concepts

All Affiliations

Oregon State University Intel (United States)University of British Columbia IBM (United States)IBM Research - Zurich

About

Rajesh Inti is an author at Oregon State University specializing in computer engineering, engineering, and signal processing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	15	18	678
2	Engineering	14	16	615
3	Computer Architecture	7	7	237
4	Electrical Engineering	6	6	171
5	Fiber Optics	1	1	18

Rajesh Inti

Publications

812

Citations

H-Index

Page 1

	Year	Citations
A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer Karthikeyan Reddy, Sachin Rao, Rajesh Inti, IEEE Journal of Solid-State Circuits Second StageEngineeringData ConverterMixed-signal Integrated CircuitAnalog Design	2012	115
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops Amr Elshazly, Rajesh Inti, Ben Young, IEEE Journal of Solid-State Circuits Hardware SecurityDpll ChipsEngineeringAnalog-to-digital ConverterClock Recovery	2013	90
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance Rajesh Inti, Wenjing Yin, Amr Elshazly, IEEE Journal of Solid-State Circuits Oscillator Clock PhasesClock RecoveryData ConverterMixed-signal Integrated CircuitAnalog Design	2011	76
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking Wenjing Yin, Rajesh Inti, Amr Elshazly, IEEE Journal of Solid-State Circuits Proportional PathRadio FrequencyHigh-frequency DeviceDigital Phase-locked LoopClock Recovery	2011	63
A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS Tawfiq Musah, James Jaussi, Ganesh Balamurugan, IEEE Journal of Solid-State Circuits EngineeringLow Profile ConnectorNm CmosChannel EqualizationMixed-signal Integrated Circuit	2014	59
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop Guanghua Shu, Saurabh Saxena, Woo‐Seok Choi, IEEE Journal of Solid-State Circuits Jitter PeakingElectrical EngineeringEngineeringClock RecoveryJitter Tolerance	2014	53
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration Amr Elshazly, Rajesh Inti, Wenjing Yin, IEEE Journal of Solid-State Circuits EngineeringAnalog-to-digital ConverterDigital Phase-locked LoopCalibration LogicDpll Peak-to-peak Jitter	2011	49
A 16mW 78dB-SNDR 10MHz-BW CT-&#x0394;&#x03A3; ADC using residue-cancelling VCO-based quantizer Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Nonlinear CircuitData ConverterMixed-signal Integrated CircuitVoltage-controlled OscillatorAnalog Design	2012	43
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS Tzu-Chien Hsueh, Ganesh Balamurugan, James Jaussi, Hardware SecurityNon-volatile MemoryEngineeringVlsi DesignMemory Configurations	2014	34
Digital clock and data recovery circuit design: Challenges and tradeoffs Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu Hardware SecurityDigital ClockElectrical EngineeringEngineeringCircuit System	2011	29

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