An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, +3

IEEE Transactions on Circuits & Systems II Express Briefs

Bang–bang Phase-frequency DetectionMinimum JitterHigh-frequency DeviceClock RecoveryMixed-signal Integrated Circuit +6

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

Sang-Hyeok Chu, Woorham Bae, Gyu-Seob Jeong, +5

IEEE Journal of Solid-State Circuits

PhotonicsEngineeringMeasured Jitter ToleranceOptical Transmission SystemAll-digital Clock +12

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Dongkyun Kim, Kibong Koo, Yongmi Kim, +22

IEEE Journal of Solid-State Circuits

Hardware SecurityPower ConsumptionDecision Feedback EqualizationVlsi DesignEngineering +12

23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Dongkyun Kim, Minsu Park, Sungchun Jang, +32

EngineeringVlsi DesignComputer ArchitectureCommand PinsHigh-speed Serdes +14

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit

Sungchun Jang, Heesoo Song, Seok-Min Ye, +1

System On ChipElectrical EngineeringEngineeringVlsi DesignClock Recovery +10

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Sung‐Yong Cho, Sungwoo Kim, Min-Seong Choo, +7

Pulse GeneratorElectrical EngineeringEngineeringRadio FrequencyAnalog-to-digital Converter +7

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-<inline-formula> <tex-math notation="LaTeX">${\rm G}_{\rm m}$ </tex-math> </inline-formula> Bias

Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, +6

IEEE Journal of Solid-State Circuits

Low-power ElectronicsGb/s 0.4Electrical EngineeringEngineeringVlsi Design +12

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

Taeho Kim, Sungchun Jang, Sungwoo Kim, +3

IEEE Transactions on Circuits & Systems II Express Briefs

Low-power ElectronicsElectrical EngineeringOn-chip Ac CouplingEngineeringVlsi Design +13

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface

Soyeong Shin, Han-Gon Ko, Sungchun Jang, +2

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, +3

Analog-to-digital ConverterRadio FrequencyHigh-frequency DeviceClock RecoveryMixed-signal Integrated Circuit +6