Sang-Hyeok Chu

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

Byoung-Joo Yoo, Dong‐Hyuk Lim, Hyonguk Pang et al. · 2020 · 57 citations

Engineering, Computer Engineering, Electrical Engineering +15

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2015 · 48 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

Sang-Hyeok Chu, Woorham Bae, Gyu-Seob Jeong et al. · IEEE Journal of Solid-State Circuits · 2015 · 47 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

Sung‐Yong Cho, Sungwoo Kim, Min-Seong Choo et al. · 2015 · 18 citations

Engineering, Electrical Engineering, Low-power Design +13

IBM POWER8 circuit design and energy optimization

Victor Zyuban, J. Friedrich, Daniel Dreps et al. · IBM Journal of Research and Development · 2015 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +17